Current Issue : July - September Volume : 2013 Issue Number : 3 Articles : 5 Articles
Apower efficient circuit topology is proposed to implement a low-voltageCMOS 2-input pass-transistorXOR gate. This design aims\r\nto minimize power dissipation and reduce transistor count while at the same time reducing the propagation delay. The XOR gate\r\nutilizes six transistors to achieve a compact circuit design and was fabricated using the 130 nmIBMCMOS process.Theperformance\r\nof the XOR circuit was validated against other XOR gate designs through simulations using the same 130 nm CMOS process. The\r\narea of the core circuit is only about 56 sq �· ??m with 1.5659 ns propagation delay and 0.2312 nW power dissipation at 0.8V supply\r\nvoltage. The proposed six-transistor implementation thus compares favorably with other existing XOR gate designs....
In this paper, a novel 12-bit current-steering binary-weighted digital-to-analog converter (DAC) based on\nnanoampere bits is designed and modified for high-definition television (HDTV) applications. As a part of a\nwidely used consumer appliance, it is aimed to be such designed to consume power as low as possible.\nHence, as a distinguished idea, prime concentration is focused on the reduction of the currents providing the\nbits of the proposed DAC. To do this, current mirrors operating in the weak inversion region are arranged to\nestablish the least significant bit (LSB) current as low as 10 nA while the power supply is also reduced to 1 V,\nresulting to an ultralow power of 52.9 �µW. Many other powerful ideas are then deliberately combined to\nmaintain both high speed and very low glitches required for HDTV application despite those ultralow currents\nand power. The result is a speed of 100 MS/s, an ultralow glitch of ?10.91 fAs, |INL| = 0.988 LSB, |DNL|\n= 0.99 LSB, and a spurious-free dynamic range of ?73 dB. These results caused the proposed DAC to execute\na distinguished overall performance (defined as figure of merit) greatly better than some other advanced\nones by outstanding ratios of 77 to 277,185. Hspice simulations with the SMIC 0.18-�µm complementary\nmetal-oxide semiconductor technology have been used to validate the proposed circuit. Performance\nevaluation of the proposed DAC versus Monte Carlo simulations and also a wide range of temperature\nvariations proved both its well mismatch insensitivity and thermal stability....
This paper presents a millimeter-wave, 60GHz frequency band planar diplexer based on substrate integrated waveguide (SIW)\r\ntechnology. Diplexer consists of a pair of 5th-order SIWbandpass channel filters with center frequencies at 59.8GHz and 62.2GHz\r\nproviding 1.67% and 1.6% relative bandwidths, respectively. SIW-to-microstrip transitions at diplexer ports enable integration in\r\na millimeter-wave transceiver front end. Measurements are in good agreement with electromagnetic simulation, reporting very\r\ngood channel isolation, small return losses, and moderate insertion losses in the passbands. The proposed SIW planar diplexer\r\nis integrated into a millimeter-wave transceiver front end for 60GHz point-to-point multigigabit wireless backhaul applications,\r\nproviding high isolation between transmit and receive channels....
Based on a 1D Poissons equation resolution, we present an analytic model of inversion charges allowing calculation of the drain\r\ncurrent and transconductance in the Metal Oxide Semiconductor Field Effect Transistor. The drain current and transconductance\r\nare described by analytical functions including mobility corrections and short channel effects (CLM, DIBL). The comparison with\r\nthe Pao-Sah integral shows excellent accuracy of the model in all inversion modes from strong to weak inversion in submicronics\r\nMOSFET. All calculations are encoded with a simple C program and give instantaneous results that provide an efficient tool for\r\nmicroelectronics users....
Testing is regarded as one of the most difficult challenges for three-dimensional integrated circuits (3D ICs). In this paper, we want\r\nto optimize the cost of TAM (test access mechanism) and the test time for 3D IC. We used both greedy and simulated annealing\r\nalgorithms to solve this optimization problem. We compare the results of two assumptions: soft-die mode and hard-die mode. The\r\nformer assumes that the DfT of dies cannot be changed, while the latter assumes that the DfT of dies can be adjusted. The results\r\nshow that thermal-aware cooptimization is essential to decide the optimal TAM and test schedule. Blindly adding TAM cannot\r\nreduce the total test cost due to temperature constraints. Another conclusion is that soft-die mode is more effective than hard-die\r\nmode to reduce the total test cost for 3D IC....
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